Simultaneous timing and power optimization is often a tough task in modern VLSI designs. A popular method to balance these two tasks is to apply multiple threshold voltages (multi-Vt) to reduce leakage power while maintaining circuit performance. In a multi-Vt design, low threshold voltage (LVT) cells are used on critical paths to improve timing, while high threshold voltage (HVT) cells are used on non-critical paths to suppress leakage power. By properly using different Vt cells, a design can achieve high performance while meeting low power requirements. A multi-Vt design can be manufactured by controlling the dopant concentration for different Vt cells by the ion implantation method.
As minimum feature sizes decrease, design rules have become more restricted, and a minimum implant area (MIA) constraint has emerged as a new challenge for the physical design flow. The MIA constraint specifies a lower bound for the areas of implant layers (implant areas for short), and an LVT/HVT cell may incur an MIA violation if any of the two implant areas is smaller than the MIA constraints.